Dual v3 mobo memory config question

[zombie67]

Everything is running the same some how. I give up. Of course, none of this is under any kind of load. That won't happen until all the updates complete sometime next month.

D'oh! I was wrong. After moving the DIMMs, now I see only half. I was up too late...

[Mumps]

If I understand it correctly, the whole idea behind the QPI (and to AMD's HT before that) is it allows the cpu's to exchange data from the memory they control with each other. In theory, with an appropriate NUMA architecture, one CPU might be able to simply lean on the other for managing all memory access. I'd just presume it would make things slower. From what zombie67 seems to be seeing, it looks like this board may support that. Even if the docs are standard Chengrish.

[Mumps]

D'oh! I was wrong. After moving the DIMMs, now I see only half. I was up too late...

Huh? You're confusing me. You see only half the RAM after moving them to 2 sticks associated with each processor? Or you were seeing half before the move and now see twice as much RAM in the more "normal" configuration?

[zombie67]

You see only half the RAM after moving them to 2 sticks associated with each processor?

Yes, that. It seems the instructions in the manual, to put all 4 around one CPU, is correct. Boggle.

[John P. Myers]

The electrical signals travel much slower than that on a PC board That figure is for "free space". But since everything is "relative" then timing issue is real regardless of the speed.

Well yes it does, but that detail wasn't that important in this context

Yes, that. It seems the instructions in the manual, to put all 4 around one CPU, is correct. Boggle.

Well...i think it's safe to say we all learned something new today, as retarded as it might be...

[Bryan]

Well yes it does, but that detail wasn't that important in this context

Well excuse me ... I'll butt out! Since you mentioned the distance of travel and that that was also the measure of RAM timing I thought it made sense. Guess not.

[John P. Myers]

Well excuse me ... I'll butt out! Since you mentioned the distance of travel and that that was also the measure of RAM timing I thought it made sense. Guess not.

Lol don't take offense. It did make sense, it's just that i was trying to keep things simple. That's all.

[John P. Myers]

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

[Al]

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

ummm..what John said. Holy crap...my wife thought I was a geek. I'll just go back to my dust bunny cleaning and hope for the best. Have a nice geek filled day!

[FourOh]

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

https://youtu.be/M9d7oG4WTyY