Dual v3 mobo memory config question

So I ended up going with the ASRock mobo. I have only 4 DIMMs to use right now. More are on the way, so eventually all 8 DIMM slots will be filled.

But until then, I will be using only the 4. All the other dual CPU mobos I have seen, say 2 go into the slots around each CPU. It can vary, either two slots next to each other, or alternating slots. But always 2 for each CPU.

This mobo says to put all 4 around just the #1 CPU, even when both CPUs are populated. Can this possibly be right? Check out page 20 of the manual.

https://dl.dropboxusercontent.com/u/...2C612%20WS.pdf

It seems to contradict their own block diagram on page 14, which implies that the DIMM sockets around CPU#1 are all for CPU#1, not shared.

Can page 20 possibly be right?

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Originally Posted by zombie67

So I ended up going with the ASRock mobo. I have only 4 DIMMs to use right now. More are on the way, so eventually all 8 DIMM slots will be filled.

But until then, I will be using only the 4. All the other dual CPU mobos I have seen, say 2 go into the slots around each CPU. It can vary, either two slots next to each other, or alternating slots. But always 2 for each CPU.

This mobo says to put all 4 around just the #1 CPU, even when both CPUs are populated. Can this possibly be right? Check out page 20 of the manual.

https://dl.dropboxusercontent.com/u/...2C612%20WS.pdf

It seems to contradict their own block diagram on page 14, which implies that the DIMM sockets around CPU#1 are all for CPU#1, not shared.

Can page 20 possibly be right?

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Yep, that's the way the manual reads. Now whether or not the manual is accurate? That I cannot say. Logic dictates if you try it though the manual is wrong, then the system just won't boot.

I'm gonna say there's a 99.9999% chance it's wrong :p

Whelp, it's running. Task manager sees all threads and all memory. No idea how, or how well. But this is a temporary situation anyway. Seriously, how messed up is this? Are all documents just crap?

"Have you ever seen a TV program, concerning a topic about which you were actually knowledgeable, spew forth anything other than total BS? I don't think I can recall one :-( It's scary!" --Malcolm Hoar

If you don't read the newspaper, you are uninformed. If you do read the newspaper, you are misinformed. -- Author unknown, commonly attributed to Mark Twain or Thomas Jefferson

Come to think of it, it's not even feasible to run the motherboard's circuitry to allow DIMM slots in any random location to work with a CPU socket farther away. The physical distance the DIMMs are from the CPU is very important since light only travels 11.8 inches per nanosecond, which is the unit of measure the RAM timings are based on. A slot that's too far away will be out of time with the closer slots.

The first 225 win7 updates are almost finished. Upon completion, I will try using their 2 DIMM config, but with each CPU, and see what happens.

I understand why task manager would see all memory, because technically it is all there. Same with all cores. They are all there, somewhere. But i doubt you could actually use a core on CPU2 unless Win7 uses the swap file for everything.

Everything is running the same some how. I give up. Of course, none of this is under any kind of load. That won't happen until all the updates complete sometime next month.

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Originally Posted by John P. Myers

Come to think of it, it's not even feasible to run the motherboard's circuitry to allow DIMM slots in any random location to work with a CPU socket farther away. The physical distance the DIMMs are from the CPU is very important since light only travels 11.8 inches per nanosecond, which is the unit of measure the RAM timings are based on. A slot that's too far away will be out of time with the closer slots.

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The electrical signals travel much slower than that on a PC board :D That figure is for "free space". But since everything is "relative" then timing issue is real regardless of the speed.

double post

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Originally Posted by zombie67

Everything is running the same some how. I give up. Of course, none of this is under any kind of load. That won't happen until all the updates complete sometime next month.

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D'oh! I was wrong. After moving the DIMMs, now I see only half. I was up too late...

If I understand it correctly, the whole idea behind the QPI (and to AMD's HT before that) is it allows the cpu's to exchange data from the memory they control with each other. In theory, with an appropriate NUMA architecture, one CPU might be able to simply lean on the other for managing all memory access. I'd just presume it would make things slower. From what zombie67 seems to be seeing, it looks like this board may support that. Even if the docs are standard Chengrish. :)

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Originally Posted by zombie67

D'oh! I was wrong. After moving the DIMMs, now I see only half. I was up too late...

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Huh? You're confusing me. You see only half the RAM after moving them to 2 sticks associated with each processor? Or you were seeing half before the move and now see twice as much RAM in the more "normal" configuration?

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Originally Posted by Mumps

You see only half the RAM after moving them to 2 sticks associated with each processor?

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Yes, that. It seems the instructions in the manual, to put all 4 around one CPU, is correct. Boggle.

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Originally Posted by Bryan

The electrical signals travel much slower than that on a PC board :D That figure is for "free space". But since everything is "relative" then timing issue is real regardless of the speed.

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Well yes it does, but that detail wasn't that important in this context :p

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Originally Posted by Zombie67

Yes, that. It seems the instructions in the manual, to put all 4 around one CPU, is correct. Boggle.

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Well...i think it's safe to say we all learned something new today, as retarded as it might be...

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Originally Posted by John P. Myers

Well yes it does, but that detail wasn't that important in this context :p

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Well excuse me ... I'll butt out! Since you mentioned the distance of travel and that that was also the measure of RAM timing I thought it made sense. Guess not.

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Originally Posted by Bryan

Well excuse me ... I'll butt out! Since you mentioned the distance of travel and that that was also the measure of RAM timing I thought it made sense. Guess not.

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Lol don't take offense. It did make sense, it's just that i was trying to keep things simple. That's all.

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

Quote:

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Originally Posted by John P. Myers

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

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ummm..what John said. Holy crap...my wife thought I was a geek. I'll just go back to my dust bunny cleaning and hope for the best. Have a nice geek filled day!

Quote:

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Originally Posted by John P. Myers

Alright. Since i'm back home now and fell guilty about half-assing electrical current flow data, he's the more complex answer:

Yes, an electrical signal travels much slower than the speed of light in a circuit board as Bryan said. For the RAM traces in the top PCB layer, it is generally around 60% (~50% for sub-layers), meaning the signal only travels about 7.08" in 1 ns. And just for completeness, i'll also point out that while the electrical signal travels from positive to negative in a DC circuit, the electrons themselves travel from negative to positive and move only about 0.2 mm/s.

So, in DDR4 2133MHz ECC RAM with a standard CL of 15, you have 1 clock tick every ~0.94ns (0.83ns @ 2400MHz supported by the Xeon v4 CPUs), which is enough time for the electrical signal to travel 6.656" (5.88" @ 2400MHz). Of course, the MHz speed of the DDR bus is half the stated Mhz speed, but since it can spit out data twice per clock, it's effectively the same, because the data is spit out at the start of the clock cycle, then again halfway through, not twice at the same time.

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@-) https://youtu.be/M9d7oG4WTyY