Quote Originally Posted by pinhodecarlos View Post
It will fail due to memory bottleneck and function of the size you are LLRing. Probably you will only be running 80% of the cores.
These chips have dual memory controllers so I doubt there would be any bottleneck, especially in a 2P setup. I ran SRBase and never noticed any issues. I'm currently running 28 CEP2 beta tasks at WCG which are highly memory and HDD intensive. They're all running @ 99+% efficiency. I'll post a screen shot if anyone might be interested.